6.25 Gbps multi-rate, multi-lane, SerDes macro IP

CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation datasheet

Quadruple 2-Input Positive-NOR Gates datasheet (Rev. B)

CD54ACT20, CD74ACT20 datasheet

datasheet

datasheet (Rev. B)

datasheet

datasheet

Analog Multiplexer and Demultiplexer datasheet (Rev. A)

datasheet

1-Line to 10-Line Clock Driver w/3-State Outputs datasheet (Rev. A)

2:12 Low Additive Jitter LVDS Buffer datasheet (Rev. D)

Dual 1:6 Low Additive Jitter LVDS Buffer datasheet (Rev. B)

Low-Voltage 1:10 LVPECL with Selectable Input Clock Driver.. datasheet

Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver datasheet (Rev. B)

3.3-V High Performance Rad-Tolerant Class V, Clock Synchronizer and Jitter Cleaner datasheet (Rev. G)

200-MHz General-Purpose Clock Buffer, PCI-X Compliant datasheet (Rev. A)

2.5-V to 3.3-V High Performance Clock Buffer datasheet

Class-V, Radiation Hardened High-Speed PWM Controller datasheet (Rev. C)

Single 9-A High Speed Low-Side MOSFET Driver With Enable datasheet (Rev. C)