逻辑 / 模拟开关

Single positive edge triggered D-type flip-flop

Single positive edge triggered D-type flip-flop

Single exclusive OR gate

Single inverter (single stage)

Single 2-input NOR gate

Single 2-input open drain NAND gate

Single inverter

Single inverter (open drain)

Single buffer (open drain)

Single 2-input AND gate

Single bus buffer (3-state)

Single bus buffer (3-state)

Single 2-input OR gate

Single positive edge triggered D-type flip-flop

Low voltage CMOS 16-bit bus buffer (3-state) with 3.6V tolerant inputs and outputs

Low voltage CMOS 16-bit bus transceiver (3-state) with 3.6V tolerant inputs and outputs

Low voltage CMOS 16-bit bus buffer (3-state inv.) with 3.6V tolerant inputs and outputs

Low voltage CMOS 16-bit bus buffer (3-state) with 3.6V tolerant inputs and outputs

Low voltage CMOS 16-bit bus transceiver (3-state) with 3.6 V tolerant inputs and outputs

16-bit dual supply bus transceiver level translator with a side series resistor