Hex D Flip-Flop with Common Clock and Reset

Quad Bus Buffer with 3‐State Control Inputs

P-Channel Logic Level Enhancement Mode Field Effect Transistor

Low voltage 0.5 &#937 max quad SPDT switch with break-before-make feature

Snubberless, logic level and standard 8 A Triacs -

12 A Snubberless™, logic level and standard Triacs

10 A Snubberless™, logic level and standard Triacs

12 A 800 V logic level Triac in TO-220AB package

Snubberless™, logic level and standard 12 A Triacs

Snubberless™, logic level and standard 16 A Triacs

Logic level 16 A Triac

16 A 800 V logic level Triac in TO-220AB package

Snubberless™, logic level and standard 16 A Triacs

6 A 800 V logic level Triac in TO-220AB package

Snubberless™, logic level and standard 8 A Triacs

8 A 800 V logic level Triac in TO-220AB package

0.8 A 600 V logic level gate thyristor SCR in TO-92 package