N-Channel Logic Level Enhancement Mode Field Effect Transistor

Single Inverter with Open

Single Non‐Inverting Buffer with Open Drain Output

Dual Schmitt-Trigger Inverter

11-bit DDR2 SDRAM MUX/bus switch with 12 Ω ON resistance

20-bit DDR SDRAM 2 : 1 MUX

Dual bidirectional bus buffer

14.318–150 MHz I2C 1:18 clock buffer

533 MHz I2C 1:6 clock buffer

_1, 0–300 MHz I 2 C 1:18 clock buffer

0–300 MHz I 2 C 1:10 clock buffer

533 MHz PCI-X clock buffer

533 MHz PCI-X clock buffer

1.8 V configurable registered buffer for DDR2 RDIMM applications

1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications

1.8 V configurable registered buffer for DDR2-667 RDIMM applications

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

1.8 V configurable registered buffer for DDR2-800 RDIMM applications

1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications