恩智浦

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver

Data Sheet

UHF 900 MHz transceiver IC

Quadruple video input processor

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder

5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs

/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

/554D Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte data sheet

/654DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder

5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs

5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs data sheet

Dual UART with 64-byte FIFO

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs

1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and 68 mode uP interface

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte FIFOs, IrDA encoder/decoder, and 68 mode uP interface

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and 68 mode μP interface