[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"part:ti:SN74AUP2G32":3},{"part":4,"mfr":13,"docs":19,"aliases":53,"alts":54,"breadcrumbs":55,"related":56,"more_from_mfr":117},{"id":5,"pn":6,"pn_norm":6,"series":7,"package":7,"lifecycle":8,"summary":9,"params":10,"features":11,"pins":7,"updated_at":12,"category_name":7,"category_name_en":7,"category_path":7},59082,"SN74AUP2G32",null,"active","Low-Power Dual 2-Input Positive-OR Gate datasheet (Rev. B)",[],[],"2026-10-11T08:07:30.858Z",{"slug":14,"name_en":15,"name_cn":16,"website":17,"is_domestic":18},"ti","Texas Instruments","德州仪器","https:\u002F\u002Fwww.ti.com",false,[20,28,37,46],{"id":5,"filename":21,"title":22,"pages":23,"size_bytes":24,"lang":7,"doc_version":7,"published_at":7,"role":25,"outline_count":26,"thumb":27},"TI-SN74AUP2G32.pdf","SN74AUP2G32 Low-Power Dual 2-Input Positive-OR Gate datasheet (Rev. B)",25,870325,"datasheet",12,"\u002Fthumbs\u002F88\u002Feb\u002F88eb133882612d07e9f8cf7decebc80c8bbe5a2425e90e66041517ba1e634203.jpg",{"id":29,"filename":30,"title":31,"pages":32,"size_bytes":33,"lang":7,"doc_version":7,"published_at":7,"role":34,"outline_count":35,"thumb":36},89554,"scea046b.pdf","Understanding Schmitt Triggers (Rev. B)",4,237938,"appnote",0,"\u002Fthumbs\u002F8f\u002Fff\u002F8fff7406704292e8e95ee016654183a6a0cb0fa999cf16bb889805513684965e.jpg",{"id":38,"filename":39,"title":40,"pages":41,"size_bytes":42,"lang":7,"doc_version":7,"published_at":7,"role":43,"outline_count":44,"thumb":45},98626,"sceu017.pdf","5-8-Logic-EVM User's Guide",7,10423090,"user_manual",9,"\u002Fthumbs\u002Fe4\u002F1b\u002Fe41b9cf88555ea07550b1497c6847842ede0a25f2036019997a5a657ffb24193.jpg",{"id":47,"filename":48,"title":49,"pages":41,"size_bytes":50,"lang":7,"doc_version":7,"published_at":7,"role":43,"outline_count":51,"thumb":52},98632,"sceu024.pdf","5-8-NL-LOGIC-EVM User's Guide",862675,10,"\u002Fthumbs\u002Ffe\u002Fab\u002Ffeabeecf30942e4282b06f140a45947cb22ade641db960845e8c21676bac70ea.jpg",[],[],[],[57,60,63,66,69,72,75,79,82,85,88,91,94,97,100,103,106,108,111,114],{"pn_display":58,"pn_norm":58,"package":7,"summary":59},"SN74AUP1G00","Low-Power Single 2-Input Positive-NAND Gate datasheet (Rev. J)",{"pn_display":61,"pn_norm":61,"package":7,"summary":62},"SN74AUP1G02","Low-Power Single 2-Input Positive-NOR Gate datasheet (Rev. I)",{"pn_display":64,"pn_norm":64,"package":7,"summary":65},"SN74AUP1G04","Low-Power Single Inverter Gate datasheet (Rev. K)",{"pn_display":67,"pn_norm":67,"package":7,"summary":68},"SN74AUP1G06","Low-Power Single Inverter With Open-Drain Outputs datasheet (Rev. E)",{"pn_display":70,"pn_norm":70,"package":7,"summary":71},"SN74AUP1G07","Low-Power Single Buffer\u002FDriver With Open-Drain Outputs datasheet (Rev. J)",{"pn_display":73,"pn_norm":73,"package":7,"summary":74},"SN74AUP1G08","Low-Power Single 2-Input Positive-AND Gate datasheet (Rev. Q)",{"pn_display":76,"pn_norm":77,"package":7,"summary":78},"SN74AUP1G08-Q1","SN74AUP1G08Q1","LOW-POWER SINGLE 2-INPUT POSITIVE AND GATE datasheet",{"pn_display":80,"pn_norm":80,"package":7,"summary":81},"SN74AUP1G125","Low-Power Single Bus Buffer Gate With 3-State Output datasheet (Rev. N)",{"pn_display":83,"pn_norm":83,"package":7,"summary":84},"SN74AUP1G126","Low-Power Single Bus Buffer Gate With Tri-State Output datasheet (Rev. G)",{"pn_display":86,"pn_norm":86,"package":7,"summary":87},"SN74AUP1G14","Low-Power Single Schmitt-Trigger Inverter datasheet (Rev. J)",{"pn_display":89,"pn_norm":89,"package":7,"summary":90},"SN74AUP1G17","Low-Power Single Schmitt-Trigger Buffer datasheet (Rev. J)",{"pn_display":92,"pn_norm":93,"package":7,"summary":25},"SN74AUP1G17-EP","SN74AUP1G17EP",{"pn_display":95,"pn_norm":95,"package":7,"summary":96},"SN74AUP1G240","Low-Power Single Inverter With 3-State Output datasheet (Rev. D)",{"pn_display":98,"pn_norm":98,"package":7,"summary":99},"SN74AUP1G32","Low-Power Single 2-Input Positive-OR Gate datasheet (Rev. K)",{"pn_display":101,"pn_norm":101,"package":7,"summary":102},"SN74AUP1G34","Low-Power Single Buffer Gate datasheet (Rev. K)",{"pn_display":104,"pn_norm":104,"package":7,"summary":105},"SN74AUP1G57","Low-Power Configurable Multiple-Function Gate datasheet (Rev. J)",{"pn_display":107,"pn_norm":107,"package":7,"summary":105},"SN74AUP1G58",{"pn_display":109,"pn_norm":109,"package":7,"summary":110},"SN74AUP1G74","Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. D)",{"pn_display":112,"pn_norm":112,"package":7,"summary":113},"SN74AUP1G79","Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. I)",{"pn_display":115,"pn_norm":115,"package":7,"summary":116},"SN74AUP1G80","Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. F)",[118,121,124,127,130,133,136,139,142,145,147,150],{"pn_display":119,"pn_norm":119,"summary":120},"TPS5430","5.5V 至 36V 输入、3A、500kHz 降压转换器",{"pn_display":122,"pn_norm":122,"summary":123},"TPS5430DDAR","5.5V 至 36V 输入、3A、500kHz 降压转换器（卷带）",{"pn_display":125,"pn_norm":125,"summary":126},"TPS5431","5.5V 至 23V 输入、3A、500kHz 降压转换器",{"pn_display":128,"pn_norm":128,"summary":129},"TLV9064","10MHz 低噪声 RRIO 四路运算放大器",{"pn_display":131,"pn_norm":131,"summary":132},"TLV9062","10MHz 低噪声 RRIO 双路运算放大器",{"pn_display":134,"pn_norm":134,"summary":135},"LM317","1.25V 至 37V 可调、1.5A 三端线性稳压器",{"pn_display":137,"pn_norm":137,"summary":138},"SN65HVD75","3.3V 半双工 RS-485 收发器 20Mbps",{"pn_display":140,"pn_norm":140,"summary":141},"SN65HVD72","3.3V 半双工 RS-485 收发器",{"pn_display":143,"pn_norm":143,"summary":144},"TLV9061","10MHz 低噪声 RRIO 单路运算放大器",{"pn_display":146,"pn_norm":146,"summary":7},"XTR111",{"pn_display":148,"pn_norm":148,"summary":149},"CC1101","Low-Power Sub-1 GHz RF Transceiver datasheet (Rev. I)",{"pn_display":151,"pn_norm":151,"summary":152},"TPS53820","Integrated Step-Down Converter with SVID Interface for Intel® CPU Power Supply datasheet"]