逻辑 / 模拟开关

Single 2-input NOR gate

Single buffer/driver with open drain

Low voltage CMOS single 2-input AND gate with 5 V tolerant input

Single bus buffer (3-state)

Single 2-input NAND gate

Single 2-input NOR gate

Single 2-input open drain NAND gate

Single 2-input AND gate

Single Schmitt inverter

Single positive edge triggered D-type flip-flop

Single buffer (open drain)

Single bus buffer (3-state)

Asynchronous parallel input or synchronous serial-in/serial-out 8-stage static shift register

Low voltage low on-resistance SPDT switch with break-before-make feature

N-Channel Logic Level Enhancement Mode Field Effect Transistor

Field Effect Transistor - N‐Channel, Logic Level, Enhancement Mode

P-Channel Logic Level Enhancement Mode Field Effect Transistor

Single 2-Input OR Gate

Single 2‐Input AND Gate

Single 2‐Input OR Gate