逻辑 / 模拟开关

Single Schmitt inverter

Single 2-input OR gate

Single D-type latch

Single positive edge triggered D-type flip-flop

Single positive edge triggered D-type flip-flop

Single exclusive OR gate

Single inverter (single stage)

Single 2-input NOR gate

Single 2-input open drain NAND gate

Single inverter

Single inverter (open drain)

Single buffer (open drain)

Single 2-input AND gate

Single bus buffer (3-state)

Single bus buffer (3-state)

Single 2-input OR gate

Single positive edge triggered D-type flip-flop

Snubberless, logic level and standard 8 A Triacs -

12 A Snubberless™, logic level and standard Triacs

10 A Snubberless™, logic level and standard Triacs