逻辑 / 模拟开关

P-Channel Logic Level Enhancement Mode Field Effect Transistor

N-Channel Logic Level Enhancement Mode Field Effect Transistor

Field Effect Transistor - N‐Channel, Logic Level, Enhancement Mode

P-Channel Logic Level Enhancement Mode Field Effect Transistor

Bus Buffer with 3‐State Output

Single 2-Input AND Gate

Single 2-Input OR Gate

Single Non‐Inverting Buffer with Open Drain Output

Single 2‐Input AND Gate

Non‐Inverting 3‐State Buffer

Non‐Inverting 3‐State Buffer

Single Inverter with Schmitt Trigger

Single Input Buffer

Single Non‐Inverting Buffer with Schmitt Trigger

Single 2‐Input OR Gate

MOSFET – Power, N‐Channel, Logic Level, SOT‐223 3.0 A, 60 V

MOSFET – Power, Dual, N-Channel, Logic Level, Dual SO8FL 60 V, 39 m , 17 A

MOSFET - Power, Single N-Channel, Logic Level, SO8FL 40 V, 0.7 mΩ, 349 A

MOSFET - Power, Single N-Channel, Logic Level, SO8FL 40 V, 0.9 mΩ, 278 A

MOSFET – Power, Single N‐Channel, Logic Level, DUAL COOL®, DFN8 5x6 40 V, 0.5 mΩ, 455 A