逻辑 / 模拟开关

Single positive edge triggered D-type flip-flop

Low voltage low on-resistance SPDT switch with break-before-make feature

N-Channel Logic Level Enhancement Mode Field Effect Transistor

Field Effect Transistor - N‐Channel, Logic Level, Enhancement Mode

P-Channel Logic Level Enhancement Mode Field Effect Transistor

Single 2-Input OR Gate

Single 2‐Input AND Gate

Single 2‐Input OR Gate

MOSFET – Power, N‐Channel, Logic Level, SOT‐223 3.0 A, 60 V

MOSFET - Power, Single N-Channel, Logic Level, DUAL COOL, DFN8 5x6

MOSFET – Power, Single N‐Channel, Logic Level, DFN5/DFNW5 30 V, 0.67 mΩ, 370 A

MOSFET – Power, Single N‐Channel, Logic Level, SOT‐23 60 V, 155 mΩ

Dual N-channel dual gate MOS-FET

Dual supply translating transceiver; auto direction sensing; 3-state

Dual supply translating transceiver; open drain; auto direction sensing

Dual supply translating transceiver; open-drain; auto direction sensing - data sheet

Dual low-ohmic single-pole single-throw analog switch

Dual low-ohmic single-pole single-throw analog switch

Dual low-ohmic single-pole single-throw analog switch

14.318–150 MHz I2C 1:18 clock buffer