逻辑门 / 触发器

0.8 A 600 V logic level gate thyristor SCR in TO-92 package

P-Channel Logic Level Enhancement Mode Field Effect Transistor

N-Channel Logic Level Enhancement Mode Field Effect Transistor

Field Effect Transistor - N‐Channel, Logic Level, Enhancement Mode

P-Channel Logic Level Enhancement Mode Field Effect Transistor

Single 2-Input AND Gate

Single 2-Input OR Gate

Single 2‐Input AND Gate

Single Inverter with Schmitt Trigger

Single 2‐Input OR Gate

MOSFET – Power, N‐Channel, Logic Level, SOT‐223 3.0 A, 60 V

MOSFET – Power, Single, N‐Channel, Logic Level, SOT‐23 60 V, 155 mΩ

MOSFET – Power, Single N‐Channel, Logic Level, SOT‐23 60 V, 155 mΩ

Dual N-channel dual gate MOS-FET

30K TrenchMOS™ logic level FET

Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder

/554D Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder

5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.) with 32-byte data sheet

/654DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder